View ADUM1200XB_6729001.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual-channel digital isolators preliminary technical data adum1200/adum1201 rev. prd december 4, 2003 information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features narrow body soic 8-lead package low power operation 5 v operation: 1.1 ma per channel max. @ 0C2 mbps 3.7 ma per channel max. @ 10 mbps 10 ma per channel max @ 30 mbps 3 v operation: 0.8 ma per channel max. @ 0C2 mbps 2.2 ma per channel max. @ 10 mbps 6.3 ma per channel max. @ 30 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 105c high data rate: dcC30 mbps (nrz) precise timing characteristics: 3 ns max. pulsewidth distortion 3 ns max. channel-to-channel matching high common-mode transient immunity: > 25 kv/s safety and regulatory approvals (pending) ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din en 60747-5-2 (vde 0884 part 2):2003-01 din en 60950 (vde 0805):2001-12;en 60950:2000 v iorm = 560 v peak applications size-critical multichannel isolation spi? interface/data converter isolation rs-232/422/485 transceiver isolation digital fieldbus isolation description the adum120x are two-channel digital isolators based on analog devices i coupler? technology. combining high speed cmos and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. by avoiding the use of leds and photodiodes, i coupler devices remove the design difficulties commonly associated with optocouplers. the typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple, i coupler digital interfaces and stable performance characteristics. the need for external drivers and other discretes is eliminated with these i coupler products. furthermore, i coupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates. the adum120x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see ordering guide). both adum120x models operate with the supply voltage of either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. in addition, the adum120x provides low pulsewidth distortion (<3 ns for crw grade), and tight channel-to-channel matching (<3 ns for crw grade). unlike other optocoupler alternatives, the adum120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. functional block diagrams figure 1. adum1200 functional block diagram figure 2. adum1201 functional block diagram gnd 2 v dd1 v dd2 gnd 1 1 8 v ia v oa decode encode 2 7 v ib v ob decode encode 3 6 4 5 gnd 2 v dd1 v dd2 gnd 1 1 8 v oa v ia encode decode 2 7 v ib v ob decode encode 3 6 4 5
adum1200/adum1201 preliminary technical data rev. prd| page 2 of 18 table of contents features .......................................................................................... 1 applications................................................................................... 1 description............................................................................. 1 functional block diagrams ...................................... 1 electrical characteristics5 v operation 1 ................................... 3 electrical characteristics3 v operation 1 ................................... 5 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation 1 ......................................................................................... 7 package characteristics.................................................................. 10 regulatory information ................................................................. 11 insulation and safety-related specifications.......................... 11 din en 60747-5-2 (vde 0884 part 2) insulation characteristics ............................................................................ 12 recommended operation conditions.......................................... 12 absolute maximum ratings ......................................................... 13 pin configurations and pin function descriptions ................. 14 pin configurations..................................................................... 14 pin function descriptions ........................................................ 14 typical performance characteristics ........................................... 15 application information................................................................ 16 pc board layout ........................................................................ 16 propagation delay-related parameters................................... 16 dc correctness and magnetic field immunity..................... 16 power consumption .................................................................. 17 outline dimensions ....................................................................... 18 ordering guide............................................................................... 18 revision history revision 0: initial version
preliminary technical data adum1200/adum1201 rev. prd | page 3 of 18 electrical characteristics5 v operation 1 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v. all min/max specifications apply over the entire recommended operation range unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. table 1. parameter symbol min. typ max unit test conditions dc specifications input supply current, per channel, quiescent i ddi(q) 0.50 0.6 ma output supply current, per channel, quiescent i ddo(q) 0.19 0.25 ma adum1200, total supply current, two channels 2 dc to 2 mbps v dd1 supply current i dd1(q) 1.1 1.4 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 0.5 0.7 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1(10) 4.3 5.5 ma 5 mhz logic signal freq. v dd2 supply current i dd2(10) 1.3 1.8 ma 5 mhz logic signal freq. 30 mbps (crw grade only) v dd1 supply current i dd1(30) 12 16 ma 15 mhz logic signal freq. v dd2 supply current i dd2(30) 3.3 4.0 ma 15 mhz logic signal freq. adum1201, total supply current, two channels 2 dc to 2 mbps v dd1 supply current i dd1(q) 0.8 1.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 0.8 1.1 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1(10) 2.8 3.5 ma 5 mhz logic signal freq. v dd2 supply current i dd2(10) 2.8 3.5 ma 5 mhz logic signal freq. 30 mbps (crw grade only) v dd1 supply current i dd1(30) 7.5 9.5 ma 15 mhz logic signal freq. v dd2 supply current i dd2(30) 7.5 9.5 ma 15 mhz logic signal freq. for all models input currents i ia , i ib C10 0.01 10 a 0 v ia , v ib v dd1 or v dd2 logic high input threshold v ih 0.7v dd v logic low input threshold v il 0.3v dd v v dd1,2 C 0.1 5.0 v i ox = C20 a, v ix = v ixh logic high output voltages v oah , v obh v dd1,2 C 0.4 4.8 v i ox = C4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl 0.2 0.4 v i ox = 4 ma, v ix = v ixl
adum1200/adum1201 preliminary technical data rev. prd| page 4 of 18 parameter symbol min. typ max unit test conditions switching specifications adum120xarw minimum pulsewidth 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 100 ns c l = 15 pf, cmos signal levels pulsewidth distortion, |t plh -t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 10 ns c l = 15 pf, cmos signal levels adum120xbrw minimum pulsewidth 3 pw 100 ns maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 50 ns c l = 15 pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change versus temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, co-directional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 15 ns c l = 15 pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels adum120xcrw minimum pulsewidth 3 pw 20 33 ns c l = 15 pf, cmos signal levels maximum data rate 4 30 50 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 45 ns c l = 15 pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change versus temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, co-directional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 15 ns c l = 15 pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 3 5 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 3 5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1/dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current, per channel 9 i ddi(d) 0.19 ma/mbps output dynamic supply current, per channel 9 i ddo(d) 0.05 ma/mbps
preliminary technical data adum1200/adum1201 rev. prd | page 5 of 18 electrical characteristics3 v operation 1 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v. all min/max specifications apply over the entire recommended operation range unless otherwise noted. all typical specifications are at t a = 25 c, v dd1 = v dd2 = 3.0 v. table 2. parameter symbol min. typ max unit test conditions dc specifications input supply current, per channel, quiescent i ddi(q) 0.26 0.35 ma output supply current, per channel, quiescent i ddo(q) 0.11 0.20 ma adum1200, total supply current, two channels 2 dc to 2 mbps v dd1 supply current i dd1(q) 0.6 1.0 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 0.2 0.5 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1(10) 2.2 3.4 ma 5 mhz logic signal freq. v dd2 supply current i dd2(10) 0.7 1.0 ma 5 mhz logic signal freq. 30 mbps (crw grade only) v dd1 supply current i dd1(30) 6.2 10.0 ma 15 mhz logic signal freq. v dd2 supply current i dd2(30) 1.8 2.5 ma 15 mhz logic signal freq. adum1201, total supply current, two channels 2 dc to 2 mbps v dd1 supply current i dd1(q) 0.4 0.8 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 0.4 0.8 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1(10) 1.5 2.2 ma 5 mhz logic signal freq. v dd2 supply current i dd2(10) 1.5 2.2 ma 5 mhz logic signal freq. 30 mbps (crw grade only) v dd1 supply current i dd1(30) 4.0 6.2 ma 15 mhz logic signal freq. v dd2 supply current i dd2(30) 4.0 6.2 ma 15 mhz logic signal freq. for all models input currents i ia , i ib C10 0.01 10 a 0 v ia , v ib , v dd1 or v dd2 logic high input threshold v ih 0.7v dd v logic low input threshold v il 0.3v dd v dd1,2 C 0.1 3.0 v i ox = C20 a, v ix = v ixh logic high output voltages v oah , v obh v dd1,2 C 0.4 2.8 v i ox = C4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl , 0.2 0.4 v i ox = 4 ma, v ix = v ixl
adum1200/adum1201 preliminary technical data rev. prd| page 6 of 18 parameter symbol min. typ max unit test conditions switching specifications adum120xarw minimum pulsewidth 3 pw 1000 ns c l = 15pf, cmos signal levels maximum data rate 4 1 mbps c l = 15pf, cmos signal levels propagation delay 5 t phl , t plh 50 100 ns c l = 15pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 40 ns c l = 15pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 10 ns c l = 15 pf, cmos signal levels adum120xbrw minimum pulsewidth 3 pw 100 ns c l = 15pf, cmos signal levels maximum data rate 4 10 mbps c l = 15pf, cmos signal levels propagation delay 5 t phl , t plh 20 60 ns c l = 15pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 3 ns c l = 15pf, cmos signal levels change versus temperature 5 ps/c c l = 15pf, cmos signal levels propagation delay skew 6 t psk 22 ns c l = 15pf, cmos signal levels channel-to-channel matching, co-directional channels 7 t pskcd 3 ns c l = 15pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 22 ns c l = 15pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 3.0 ns c l = 15 pf, cmos signal levels adum120xcrw minimum pulsewidth 3 pw 20 33 ns c l = 15pf, cmos signal levels maximum data rate 4 30 50 mbps c l = 15pf, cmos signal levels propagation delay 5 t phl , t plh 20 55 ns c l = 15pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 3 ns c l = 15pf, cmos signal levels change versus temperature 5 ps/c c l = 15pf, cmos signal levels propagation delay skew 6 t psk 16 ns c l = 15pf, cmos signal levels channel-to-channel matching, co-directional channels 7 t pskcd 3 ns c l = 15pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 16 ns c l = 15pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 3.0 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 3 5 ns c l = 15pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 3 5 ns c l = 15pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 3 ns c l = 15pf, cmos signal levels common mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1/dd2 , v cm = 1000 v, transient magnitude = 800 v common mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current, per channel 9 i ddi(d) 0.10 ma/mbps output dynamic supply current, per channel 9 i ddo(d) 0.03 ma/mbps
preliminary technical data adum1200/adum1201 rev. prd | page 7 of 18 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation 1 5 v/3 v operation: 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v. 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v. all min/max specifications apply over the entire recommended operation range unless otherwise noted. all typical specifications are at t a =25c; v dd1 = 3.0 v, v dd2 = 5 v; or v dd1 = 5 v, v dd2 = 3.0 v. table 3. parameter symbol min. typ max unit test conditions dc specifications input supply current, per channel, quiescent i ddi(q) ma 5 v/3 v operation 0.50 0.6 ma 3 v/5 v operation 0.26 0.35 ma output supply current, per channel, quiescent i ddo(q) ma 5 v/3 v operation 0.11 0.20 ma 3 v/5 v operation 0.19 0.25 ma adum1200, total supply current, two channels 2 dc to 2 mbps v dd1 supply current i dd1(q) 5 v/3 v operation 1.1 1.4 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.6 1.0 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 5 v/3 v operation 0.2 0.5 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.5 0.7 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1(10) 5 v/3 v operation 4.3 5.5 ma 5 mhz logic signal freq. 3 v/5 v operation 2.2 3.4 ma 5 mhz logic signal freq. v dd2 supply current i dd2(10) 5 v/3 v operation 0.7 1.0 ma 5 mhz logic signal freq. 3 v/5 v operation 1.3 1.8 ma 5 mhz logic signal freq. 30 mbps (crw grade only) v dd1 supply current i dd1(30) 5 v/3 v operation 12 16 ma 15 mhz logic signal freq. 3 v/5 v operation 6.2 10.0 ma 15 mhz logic signal freq. v dd2 supply current i dd2(30) 5 v/3 v operation 1.8 2.5 ma 15 mhz logic signal freq. 3 v/5 v operation 3.3 4.0 ma 15 mhz logic signal freq. adum1201, total supply current, two channels 2 dc to 2 mbps v dd1 supply current i dd1(q) 5 v/3 v operation 0.8 1.1 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.4 0.8 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 5 v/3 v operation 0.4 0.8 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.8 1.1 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1(10) 5 v/3 v operation 2.8 3.5 ma 5 mhz logic signal freq. 3 v/5 v operation 1.5 2.2 ma 5 mhz logic signal freq. v dd2 supply current i dd2(10) 5 v/3 v operation 1.5 2.2 ma 5 mhz logic signal freq. 3 v/5 v operation 2.8 3.5 ma 5 mhz logic signal freq.
adum1200/adum1201 preliminary technical data rev. prd| page 8 of 18 parameter symbol min. typ max unit test conditions 30 mbps (crw grade only) v dd1 supply current i dd1(30) 5 v/3 v operation 7.5 9.5 ma 15 mhz logic signal freq. 3 v/5 v operation 4.0 6.2 ma 15 mhz logic signal freq. v dd2 supply current i dd2(30) 5 v/3 v operation 4.0 6.2 ma 15 mhz logic signal freq. 3 v/5 v operation 7.5 9.5 ma 15 mhz logic signal freq. for all models input currents i ia , i ib C10 0.01 10 a 0 v ia ,v ib v dd1 or v dd2 logic high input threshold v ih 0.7v dd v logic low input threshold v il 0.3v dd v 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v v dd1/2 C 0.1 v dd1/2 v i ox = C20 a, v ix = v ixh logic high output voltages v oah , v obh v dd1/2 C 0.4 v dd1/2 C 0.2 v i ox = C4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal, v obl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum120xarw minimum pulsewidth 3 pw 1000 ns c l = 15pf, cmos signal levels maximum data rate 4 1 mbps c l = 15pf, cmos signal levels propagation delay 5 t phl , t plh 50 100 ns c l = 15pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 40 ns c l = 15pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15pf, cmos signal levels output rise/fall time (10%C90%) t r /t f 10 ns c l = 15 pf, cmos signal levels adum120xbrw minimum pulsewidth 3 pw 100 ns maximum data rate 4 10 mbps c l = 15pf,cmos signal levels c l = 15pf, cmos signal levels propagation delay 5 t phl , t plh 15 55 ns c l = 15pf, cmos signal levels pulsewidth distortion, |t plh C t phl | 5 pwd 3 ns c l = 15pf, cmos signal levels change versus temperature 5 ps/c c l = 15pf, cmos signal levels propagation delay skew 6 t psk 22 ns c l = 15pf, cmos signal levels channel-to-channel matching, co-directional channels 7 t pskcd 3 ns c l = 15pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 22 ns c l = 15pf, cmos signal levels output rise/fall time (10-90%) t r /t f c l = 15pf, cmos signal levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns adum120xcrw minimum pulsewidth 3 pw 20 33 ns maximum data rate 4 30 50 mbps c l = 15pf, cmos signal levels c l = 15pf, cmos signal levels propagation delay 5 t phl , t plh 20 50 ns c l = 15pf, cmos signal levels pulsewidth distortion, |t plh -t phl | 5 pwd 3 ns c l = 15pf, cmos signal levels change versus temperature 5 ps/c c l = 15pf, cmos signal levels propagation delay skew 6 t psk 15 ns c l = 15pf, cmos signal levels channel-to-channel matching, co-directional channels 7 t pskcd 3 ns c l = 15pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 15 ns c l = 15pf, cmos signal levels output rise/fall time (10-90%) t r /t f c l = 15pf, cmos signal levels
preliminary technical data adum1200/adum1201 rev. prd | page 9 of 18 parameter symbol min. typ max unit test conditions 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns for all models output disable propagation delay (high/low to high impedance) t phz , t plh 3 5 ns c l = 15pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 3 5 ns c l = 15pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1/dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input dynamic supply current, per channel 9 i ddi(d) 5 v/3 v operation 0.19 ma/mbps 3 v/5 v operation 0.10 ma/mbps output dynamic supply current, per channel 9 i ddi(d) 5 v/3 v operation 0.03 ma/mbps 3 v/5 v operation 0.05 ma/mbps notes 1 all voltages are relative to their respective ground. 2 supply current values are for both channels comb ined running at identical data rates. output supply current values are specifie d with no output load present. the supply current associated with an individual ch annel operating at a given data rate may be calculated as described in the power consumption sect ion on page 17. see figure 6 through figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see figure 9 through figure 11 for total i dd1 and i dd2 supply currents as a function of data rate for adum1200 and adum1201 channel configurations. 3 the minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl and/or t plh that will be measured between units at the s ame operating temperature, supply voltages, and output load within the recommended operating conditions. 7 co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two chann els with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute va lue of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8v dd2 . cm l is the maximum common-mod e voltage slew rate than can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 6 through figure 8 for information on per-channel supply current for unloaded and loaded conditions. see power consumption section on page 17 for guidance on calc ulating per-channel supply current for a given data rate.
adum1200/adum1201 preliminary technical data rev. prd| page 10 of 18 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input-output) 1 r i-o 10 12 ? capacitance (input-output) 1 c i-o 1.0 pf f = 1 mhz input capacitance c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 46 c/w ic junction-to-case thermal resistance, side 2 jco 41 c/w thermocouple located at center of package underside note 1 device considered a two -terminal device: pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. 1 input capacitance is from any input data pin to ground.
preliminary technical data adum1200/adum1201 rev. prd | page 11 of 18 regulatory information the adum120x will be approved by the following organizations upon product release: table 5. ul csa vde recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to: din en 60747-5-2 (vde 0884 part 2):2003-01 2 din en 60950 (vde 0805):2001-12; en 60950:2000 notes 1 in accordance with ul1577, each ad um120x is proof tested by applying an insulation test vo ltage 3000 v rms for 1 second (curr ent leakage detectio n limit = 5 a) 2 in accordance with din en 60747-5-2, each adum120x is proof tested by applying an insulation test voltage 1050 v peak for 1 s econd (partial discharge detection limit = 5 pc). insulation and safety-related specifications table 6. parameter symbol value unit conditions rated dielectric insulation volt age 2500 v rms 1 minute duration. minimum external air gap (clearance) l(i01) 4.90 min. mm measured from input termin als to output terminals, shortest distance through air. minimum external tracking (creepage) l(i02) 4.01 min. mm measured from input termin als to output terminals, shortest distance path along body. minimum internal gap (internal clearance) 0.017 min. mm insulation distance through insulation. tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1. isolation group iiia material gr oup (din vde 0110, 1/89, table 1).
adum1200/adum1201 preliminary technical data rev. prd| page 12 of 18 din en 60747-5-2 (vde 0884 part 2) insulation characteristics table 7. description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 400 v rms iCiv iCiii iCii climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input to output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input to output test voltage, method a after environmental tests subgroup 1) v iorm x 1.6 = v pr , t m = 60 sec, partial discharge < 5p c after input and/or safe ty test subgroup 2/3) v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5p c v pr 896 672 v peak v peak highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety-limiting values (max imum value allowed in the event of a failure, also see thermal derating curve, figure 3) case temperature side 1 current side 2 current t s i s1 i s2 150 265 335 c ma ma insulation resistance at t s , v io = 500 v r s >10 9 ? this isolator is suitable for basic isolation only within the safety limit data. maintenance of the safety data shall be ensu red by means of protective circuits. "*" marking on packages denotes din en 60747-5-2 approval for 560 v peak working voltage. 0 20 40 60 80 100 120 140 160 180 200 0 50 100 150 200 case temperature (deg. c) safety-limiting current (ma) side #1 side #2 figure 3. thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 recommended operation conditions parameter symbol min. max. unit operating temperature t a C40 +105 c supply voltages 1 v dd1,2 2.7 5.5 v input signal rise and fall times 1.0 ms notes 1 all voltages are relative to their respective ground. see the dc correctness and magnetic field immunity section on page 16 for information on immunity to external magnetic fields.
preliminary technical data adum1200/adum1201 rev. prd | page 13 of 18 absolute maximum ratings parameter symbol min. max. unit storage temperature t st C55 150 c ambient operating temperature t a C40 100 c supply voltages 1 v dd1, v dd2 C0.5 7.0 v input voltage 1, 2 v ia, v ib, v ic , v e1 , v e2 C0.5 v ddi + 0.5 v output voltage 1, 2 v oa, v ob, v oc C0.5 v ddo + 0.5 v average output current, per pin 3 i o -35 35 ma common-mode transients 4 -100 +100 kv/ s notes 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. 3 see figure 3 for maximum rated current values for various temperatures. 4 refers to common-mode transients across the insulation barrier. common-mode transients exceeding the absolute maximum rating may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those listed in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ambient tempera ture = 25c unless otherwise noted. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 8. adum1200 truth table (positive logic) v ia input v ib input v dd1 state v dd2 state v oa output v ob output note h h powered powered h h l l powered powered l l h l powered powered h l l h powered powered l h x x unpowered powered h h outputs returns to input state within 1 s of v ddi power restoration. x x powered unpowered indeterminate indeterminate outputs returns to input state within 1 s of v ddo power restoration. table 9. adum1201 truth table (positive logic) v ia input v ib input v dd1 state v dd2 state v oa output v ob output note h h powered powered h h l l powered powered l l h l powered powered h l l h powered powered l h x x unpowered powered indeterminate h outputs returns to input state within 1 s of v ddi power restoration. x x powered unpowered h indeterminate outputs returns to input state within 1 s of v ddo power restoration.
adum1200/adum1201 preliminary technical data rev. prd| page 14 of 18 pin configurations and pi n function descriptions pin configurations figure 4. dum1200 pin configuration figure 5. adum1201 pin configuration pin function descriptions table 9. adum1200 pin function descriptions pin no. mnemonic function 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 v ia logic input a. 3 v ib logic input b. 4 gnd 1 ground 1. ground reference for isolator side 1. 5 gnd 2 ground 2. ground reference for isolator side 2. 6 v ob logic output b. 7 v oa logic output a. 8 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v. table 10. adum1201 pin function descriptions pin no. mnemonic function 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 v oa logic output a. 3 v ib logic input b. 4 gnd 1 ground 1. ground reference for isolator side 1. 5 gnd 2 ground 2. ground reference for isolator side 2. 6 v ob logic output b. 7 v ia logic input a. 8 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v. v dd2 gnd 2 v oa (not to scale) 8 7 6 5 1 2 3 4 v dd1 v ia gnd 1 v ob top v ie w adum 1200 v ib gnd 2 v oa top v ie w (not to scale) 8 7 6 5 1 2 3 4 v dd1 v ia gnd 1 v dd2 v ob adum 1201 v ib
preliminary technical data adum1200/adum1201 rev. prd | page 15 of 18 typical performance characteristics 0 2 4 6 8 10 0102030 data rate - mbps current/channel - ma 5v 3v figure 6. typical input supply current per channel vs. data rate for 5 v and 3 v operation. 0 1 2 3 4 0102030 data rate - mbps current/channel - ma 5v 3v figure 7. typical output supply current per channel vs. data rate for 5 v and 3 v operation (no output load) 0 1 2 3 4 0102030 data rate - mbps current/channel - ma 5v 3v figure 8. typical output supply current per channel vs. data rate for 5 v and 3 v operation (15 pf output load) 0 5 10 15 20 0102030 data rate - mbps current - ma 5v 3v figure 9. typical adum1200 v dd1 supply current vs. data rate for 5 v and 3 v operation. 0 1 2 3 4 0102030 data rate - mbps current - ma 5v 3v figure 10. typical adum1200 v dd2 supply current vs. data rate for 5 v and 3 v operation. 0 2 4 6 8 10 0102030 data rate - mbps current - ma 5v 3v figure 11. typical adum1201 v dd1 v dd2 supply current vs. data rate for 5 v and 3 v operation.
adum1200/adum1201 preliminary technical data rev. prd| page 16 of 18 application information pc board layout the adum120x digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins. the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. propagation delay-related parameters propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. the propagation delay to a logic low output may differ from the propagation delay to a logic high. input (v ix ) output (v ox ) t plh t phl 50% 50% 03787-0-016 figure 12. propagation delay parameters pulsewidth distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signals timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs among channels within a single adum120x component. propagation delay skew refers to the maximum amount the propagation delay differs among multiple adum120x components operated under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and is therefore either set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than 2 s, a periodic set of "refresh" pulses indicative of the correct input state are sent to ensure "dc correctness" at the output. if the decoder receives no pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 8) by the watchdog timer circuit. the adum120x is extremely immune to external magnetic fields. the limitation on the adum120xs magnetic field immunity is set by the condition in which induced voltage in the transformers receiving coil is sufficiently large to either falsely set or reset the decoder. the analysis below defines the conditions under which this may occur. the 3 v operatin g condition of the adum120x is examined as it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by: v = ( Cd/dt ) r n 2 ; n = 1, 2,, n where: is magnetic flux density (gauss) n is the number of turns in the receiving coil r n is the radius of the n th turn in the receiving coil (cm) given the geometry of the receiving coil in the adum120x and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in below in figure 13. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 03787-0-017 figure 13. maximum allowable external magnetic flux density. for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and will not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst case polarity) it would reduce the received pulse from > 1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum120x transformers. figure 14 expresses these allowable current magnitudes as a function of frequency for selected distances. as can be seen, the adum120x is extremely immune and can be affected
preliminary technical data adum1200/adum1201 rev. prd | page 17 of 18 only by extremely large currents operated at high frequency and very close to the component. for the 1 mhz example noted, one would have to place a 0.5 ka current 5 mm away from the adum120x to affect the components operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 03787-0-018 figure 14. maximum allowable current for various current-to-adum120x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum120x isolator is a function of the supply voltage, the channels data rate, and the channels output load. for each input channel, the supply current is given by: i ddi = i ddi(q) f 0.5 f r i ddi = i ddi(d) (2 f C f r ) + i ddi(q) f > 0.5 f r for each output channel, the supply current is given by: i ddo = i ddo(q) f 0.5 f r i ddo = ( i ddo(d) + 10 6 c l v ddo ) (2 f C f r ) + i ddo(q) f > 0.5 f r where i ddi(d) , i ddo(d) are the input and output dynamic supply currents per channel (ma/mbps) c l is output load capacitance (pf) v ddo is the output supply voltage (v) f is the input logic signal frequency (mhz, half of the input data rate, nrz signaling) f r is the input stage refresh rate (mbps) i ddi(q) , i ddo(q) are the specified input and output quiescent supply currents (ma) to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to i dd1 and i dd2 are calculated and totaled. figure 6 and figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. figure 8 provides per- channel supply current as a function of data rate for a 15 pf output condition. figure 9 through figure 11 provide total i dd1 and i dd2 supply current as a function of data rate for adum1200 and adum1201 channel configurations.
adum1200/adum1201 preliminary technical data rev. prd| page 18 of 18 outline dimensions figure 15. 8-lead standard small outline package [soic] narrow body (r-8) ordering guide table 11. ordering guide model number of inputs, v dd1 side number of inputs, v dd2 side max. data rate (mbps) max. propagation delay, 5 v (ns) max. pulsewidth distortion (ns) channel-to-channel matching, co-directional channels (ns) package description adum1200ar* 2 0 1 100 40 40 8-lead narrow body soic adum1200br* 2 0 10 50 3 3 8-lead narrow body soic adum1200cr* 2 0 30 45 3 3 8-lead narrow body soic adum1201ar* 1 1 1 100 40 40 8-lead narrow body soic adum1201br* 1 1 10 50 3 3 8-lead narrow body soic adum1201cr* 1 1 30 45 3 3 8-lead narrow body soic note * tape and reel is available. the a ddition of an -rl7 suff ix designates a 7 (1000 un its) tape and reel option ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. c03787C0C8/03(0)
analog devices: adum1200: product page: package/price information adi home adum1200 description data sheets selection tables technical library product highlights package/price information order samples all design resources package/price info for detailed packaging information, please select the data sheets button. price and availability section pricing displayed for evaluation boards and kits is based on 1-piece pricing. model status package description pin count temperature range price* (100-499) adum1200ar pre-release soic 150 mil 8 industrial - adum1200arz pre-release soic 150 mil 8 industrial - adum1200br pre-release soic 150 mil 8 industrial - adum1200brz pre-release soic 150 mil 8 industrial - adum1200cr pre-release soic 150 mil 8 industrial - adum1200crz pre-release soic 150 mil 8 industrial - adum1200xa production soic 150 mil 8 industrial - ADUM1200XB production soic 150 mil 8 industrial - adum1200xc production soic 150 mil 8 industrial - pricing is not available for pre-release parts, please contact: /salesdir/>sales and distributors privacy | about this site | contact adi | site map | registration ? 1995-2004 analog devices, inc. all rights reserved. http://www.analog.com/analog_root/productpage/p...526level3%253d%25252d1%2526pdbind%253dm,00.html [3/17/2004 12:12:17 pm]

▲Up To Search▲

Price & Availability of ADUM1200XB

	To Download ADUM1200XB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .